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| preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s 16-mbit (2048 k 8/102 4 k 16/512 k 32) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-67793 rev. *l revised november 5, 2014 features 16-mbit nonvolatile static random access memory (nvsram) ? 25-ns, 30-ns and 45-ns access times ? internally organized as 2048 k 8 (cy14x116l), 1024 k 16 (cy14x116n), 512 k 32 (cy14x116s) ? hands-off automatic store on power-down with only a small capacitor ? store to quantumtrap nonvolatile elements is initiated by software, device pin, or autostore on power-down ? recall to sram initiated by software or power-up high reliability ? infinite read, write, and recall cycles ? 1 million store cycles to quantumtrap ? data retention: 20 years sleep mode operation low power consumption ? active current of 75 ma at 45 ns ? standby mode current of 650 ? a ? sleep mode current of 10 ? a operating voltages: ? cy14b116x: v cc = 2.7 v to 3.6 v ? cy14e116x: v cc = 4.5 v to 5.5 v industrial temperature: ?40 ? c to +85 ? c packages ? 44-pin thin small-outline package (tsop ii) ? 48-pin thin small-outline package (tsop i) ? 54-pin thin small-outline package (tsop ii) ? 165-ball fine-pitch ball grid array (fbga) package restriction of hazardous substances (rohs) compliant offered speeds ? 44-pin tsop ii: 25 ns and 45 ns ? 48-pin tsop i: 30 ns and 45 ns ? 54-pin tsop ii: 25 ns and 45 ns ? 165-ball fbga: 25 ns and 45 ns functional description the cypress cy14x116l/cy14x116n/cy14x116s is a fast sram, with a nonvolatile element in each memory cell. the memory is organized as 2048 k bytes of 8 bits each or 1024 k words of 16 bits each or 512 k words of 32 bits each. the embedded nonvolatile elements incorporate quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram can be read and written an infinite number of times. the nonvolatile data residing in the nonvolatile elements do not change when data is written to the sram. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power-down. on power-up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. for a complete list of related documentation, click here .
preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 2 of 36 control logic ce we oe software detect hsb zz sleep mode control power control store / recall control static ram array 4096 x 4096 quantumtrap 4096 x 4096 store recall column io column decoder sense amps input buffers row decoder dq - v cap v cc output buffers zz b 0 dq 31 a - 2 a 14 a b b b c b d /ble /bhe a - 0 a 11 a - 12 a 20 a - 12 a 20 4 logic block diagram [1, 2, 3] notes 1. address a 0 - a 20 for 8 configuration, address a 0 - a 19 for 16 configuration and address a 0 - a 18 for 32 configuration. 2. data dq 0 - dq 7 for 8 configuration, data dq 0 - dq 15 for 16 configuration and data dq 0 - dq 31 for 32 configuration. 3. ble , bhe are applicable for 16 configuration and b a , b b, b c, b d are applicable for 32 configuration only. 4. tsop ii package is offered in single ce . tsop i and bga packages are offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 3 of 36 contents pinouts .............................................................................. 4 pin definitions .................................................................. 7 device operation .............................................................. 8 sram read ................................................................ 8 sram write................................................................. 8 autostore operation (power-dow n)............................ 8 hardware store (hsb) operation............................ 9 hardware recall (power-up) . ................................. 9 software store......................................................... 9 software recall ....................................................... 9 sleep mode ............................................................... 10 preventing autostore ................................................ 12 data protection.......................................................... 12 maximum ratings........................................................... 13 operating range............................................................. 13 dc electrical characteristics ........................................ 13 data retention and endurance ..................................... 14 capacitance .................................................................... 14 thermal resistance........................................................ 14 ac test conditions ........................................................ 15 ac switching characteristics ....................................... 16 autostore/power-up recall characteristics............ 20 sleep mode characteristics........................................... 21 software controlled store and recall characteristics................................................................ 22 hardware store characteristics................................. 23 truth table for sram operations................................ 24 for 8 configuration ................................................. 24 for 8 configuration ................................................. 24 for 16 configuration ............................................... 24 for 16 configuration ............................................... 25 for 32 configuration ............................................... 25 ordering information...................................................... 26 ordering code definitions ...... ................................... 27 package diagrams.......................................................... 28 acronyms ........................................................................ 32 document conventions ................................................. 32 units of measure ....................................................... 32 document history page ................................................. 33 sales, solutions, and legal information ...................... 36 worldwide sales and design supp ort............. .......... 36 products .................................................................... 36 psoc? solutions ...................................................... 36 cypress developer community................................. 36 technical support .................. ................................... 36 preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 4 of 36 pinouts figure 1. pin diagram: 44-pin tsop ii (8) figure 2. pin diagram: 54-pin tsop ii (16) figure 3. pin diagram: 48-pin tsop i (8) nc a 8 nc nc v ss dq 6 dq 5 dq 4 v cc a 13 dq 3 a 12 dq 2 dq 1 dq 0 oe a 9 ce a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 nc we dq 7 hsb nc v ss v cc v cap nc (x8) a 17 a 18 a 20 [6] dq 7 dq 6 dq 5 dq 4 v cc dq 3 dq 2 dq 1 dq 0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 oe ce v cc nc v ss a 9 nc a 18 54 53 52 51 49 50 hsb bhe ble dq 15 dq 14 dq 13 dq 12 v ss dq 11 dq 10 dq 9 dq 8 (x16) nc nc nc nc a 16 a 17 a 19 top view (not to scale) 54 - tsop ii 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 we ce 2 v cap nc nc a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 hsb a dq 7 nc dq 6 nc dq 5 nc dq 4 nc dq 3 nc dq 2 dq 1 dq 0 oe ce 1 a 0 v ss v cc v ss nc 48 - tsop i (x8) (not to s cal e) top view nc nc 20 [5] note 5. address expansion for 32-mbit. nc pin not connected to die. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 5 of 36 figure 4. pin diagram: 48-pin tsop i (16) figure 5. pin diagram: 165-ball fbga (16) 1 2 3 4 5 6 7 8 9 10 11 a nc a 6 a 8 we ble ce 1 nc oe a 5 a 3 nc b nc dq 0 dq 1 a 4 bhe ce 2 nc a 2 nc nc nc c zz nc nc v ss a 0 a 7 a 1 v ss nc dq 15 dq 14 d nc dq 2 nc v ss v ss v ss v ss v ss nc nc nc e nc v cap nc v cc v ss v ss v ss v cc nc dq 13 nc f nc dq 3 nc v cc v cc v ss v cc v cc nc nc dq 12 g hsb nc nc v cc v cc v ss v cc v cc nc nc nc h nc nc v cc v cc v cc v ss v cc v cc v cc nc nc j nc nc nc v cc v cc v ss v cc v cc nc dq 8 nc k nc nc dq 4 v cc v cc v ss v cc v cc nc nc nc l nc dq 5 nc v cc v ss v ss v ss v cc nc nc dq 9 m nc nc nc v ss v ss v ss v ss v ss nc dq 10 nc n nc dq 6 dq 7 v ss a 11 a 10 a 9 v ss nc nc nc p nc nc nc a 13 a 19 nc a 18 a 12 nc dq 11 nc r nc nc a 15 nc a 17 nc a 16 nc [6] a 14 nc nc pinouts (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 we ce 2 v cap bhe ble a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 hsb dq 15 dq 7 dq dq 6 dq dq 5 dq dq 4 dq dq 3 dq dq 2 dq 1 dq 0 oe ce 1 a 0 v ss v cc v ss nc 48 - tsop i (x16) (not to s cal e) top view dq 8 dq 9 10 11 12 13 14 6 note 6. address expansion for 32-mbit. nc pin not connected to die. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 6 of 36 figure 6. pin diagram: 165-ball fbga (32) 1 2 3 4 5 6 7 8 9 10 11 a nc a 6 a 8 we b a ce 1 b c oe a 5 a 3 nc b nc dq 0 dq 1 a 4 b b ce 2 b d a 2 nc nc dq 31 c zz nc dq 4 v ss a 0 a 7 a 1 v ss nc dq 27 dq 26 d nc dq 2 dq 5 v ss v ss v ss v ss v ss nc nc dq 30 e nc v cap dq 6 v cc v ss v ss v ss v cc nc dq 25 dq 29 f nc dq 3 dq 7 v cc v cc v ss v cc v cc nc nc dq 24 g hsb nc dq 12 v cc v cc v ss v cc v cc nc nc dq 28 h nc nc v cc v cc v cc v ss v cc v cc v cc nc nc j nc nc dq 13 v cc v cc v ss v cc v cc nc dq 20 dq 19 k nc nc dq 8 v cc v cc v ss v cc v cc nc nc dq 18 l nc dq 9 dq 14 v cc v ss v ss v ss v cc nc nc dq 21 m nc nc dq 15 v ss v ss v ss v ss v ss nc dq 22 dq 17 n nc dq 10 dq 11 v ss a 11 a 10 a 9 v ss nc nc dq 16 p nc nc nc a 13 nc nc a 18 a 12 nc dq 23 nc r nc nc a 15 nc a 17 nc a 16 nc [7] a 14 nc nc pinouts (continued) note 7. address expansion for 32-mbit. nc pin not connected to die. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 7 of 36 pin definitions pin name i/o type description a 0 ? a 20 input address inputs. used to select one of the 2,097,15 2 bytes of the nvsram fo r the 8 configuration. a 0 ? a 19 address inputs. used to select one of the 1,048,57 6 words of the nvsram fo r the 16 configuration. a 0 ? a 18 address inputs. used to select one of the 524,288 words of the nvsram fo r the 32 configuration. dq 0 ? dq 7 input/output bidirectional data i/o lines for the 8 configuration . used as input or output lines depending on operation. dq 0 ? dq 15 bidirectional data i/o lines for the 16 configuration . used as input or output lines depending on operation. dq 0 ? dq 31 bidirectional data i/o lines for 32 configuration . used as input or output lines depending on operation. we input write enable input, active low . when selected low, data on the i/o pins is written to the specific address location. ce input chip enable input in tsop ii package, active low . when low, selects the chip. when high, deselects the chip. ce 1, ce 2 chip enable input in fbga package. the device is selected and a memory access begins on the falling edge of ce 1 (while ce 2 is high) or the rising edge of ce 2 (while ce 1 is low). oe input output enable, active low. the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. ble /b a [8] input byte enable, active low . when selected low, enables dq 7 ?dq 0 . bhe /b b [8] input byte enable, active low . when selected low, enables dq 15 ?dq 8 . b c [8] input byte enable, active low . when selected low, enables dq 23 ?dq 16 . b d [8] input byte enable, active low . when selected low, enables dq 31 ?dq 24 . zz [9] input sleep mode enable. when the zz pin is pulled low, the device enters a low-power sleep mode and consumes the lowest power. since th is input is logically and?ed with ce , zz must be high for normal operation. v cc power supply power supply inputs to the device . v ss power supply ground for the device . must be connected to ground of the system. hsb input/output hardware store busy (hsb ) .when low, this output indicates t hat a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor k eeps this pin high (external pull-up resistor connection optional). v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. nc nc no connect . die pads are not connected to the package pin. notes 8. ble , bhe are applicable for 16 configuration and b a , b b, b c, b d are applicable for 32 configuration only. 9. sleep mode feature is offered in 165-ball fbga package only. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 8 of 36 device operation the cy14x116l/cy14x116n/cy14x116s nvsram is made up of two functional components paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the stor e operation) automatically at power-down, or from the nonvol atile cell to the sram (the recall operation) on power-up. both the store and recall operations are also available under software control. using this unique architecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14x116l/cy14x116n/ cy14x116s supports infinite reads and writes to the sram. in addition, it provides infinite re call operations from the nonvol- atile cells and up to 1 million store operations. see the truth table for sram operations on page 24 for a complete description of read and write modes. sram read the cy14x116l/cy14x116n/cy14x116s performs a read cycle whenever ce and oe are low, and we , zz , and hsb are high. the address specified on pins a 0 ?a 20 or a 0 ?a 19 or a 0 ?a 18 determines which of the 2,097,152 data bytes or 1,048,576 words of 16 bits or 524 ,288 words of 32 bits each are accessed. byte enables (ble , bhe ) determine which bytes are enabled to the output, in the case of 16-bit words and byte enables (b a , b b, b c, b d ) determine which bytes are enabled to the output, in the case of 32-bit words. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the r ead is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data output repeatedly responds to address changes within the t aa access time without the need fo r transitions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycl e. the data on the common i/o pins dq 0 ?dq 31 is written into the memory if it is valid t sd before the end of a we -controlled write or before the end of a ce -controlled write. the byte enable inputs (ble , bhe determine which bytes are written, in the case of 16-bit words and byte enable inputs (b a , b b, b c, b d ) determine which bytes are written, in the case of 32-bit words. keep oe high during the entire write cycle to avoid data bus contention on the common i/o lines. if oe is left low, the internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation (power-down) the cy14x116l/cy14x116n/cy14x116s stores data to the nonvolatile quantumtrap cells using one of the three storage operations. these three operations are: hardware store, activated by the hsb ; software store, activated by an address sequence; autostore, on device power-down. the autostore operation is a unique feature of nvsram and is enabled by default on the cy14x116l/cy14x116n/cy14x116s. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a store operation during power-down. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc and a store operation is initiated with power provided by the v cap capacitor. note if the capacitor is not connected to the v cap pin, autostore must be disabled using the soft sequence specified in the section preventing autostore on page 12 . if autostore is enabled without a capacitor on the v cap pin, the device attempts an autostore operation without sufficient char ge to complete the store. this corrupts the data stored in the nvsram. figure 7. autostore mode figure 7 shows the proper connection of the storage capacitor (v cap ) for the automatic stor e operation. refer to dc electrical characteristics on page 13 for the size of the v cap . the voltage on the v cap pin is driven to v vcap by a regulator on the chip. a pull-up resistor should be placed on we to hold it inactive during power-up. this pull-up resi stor is only effective if the we signal is in tristate during power-up. when the nvsram comes out of power-up-recall, the ho st microcontroller must be active or the we held inactive until the host microcontroller comes out of reset. to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place (which sets a write latch) since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. 0.1 uf v cc v cap we v cap v ss v cc 10 k : preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 9 of 36 hardware store (hsb ) operation the cy14x116l/cy14x116n/cy14x116s provides the hsb pin to control and acknowledge the store operations. the hsb pin is used to request a hardware store cycle. when the hsb pin is driven low, the device conditionally initiates a store operation after t delay . a store cycle begins only if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver (an internal 100-k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation, hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by an internal 100-k ? pull-up resistor. sram write operations that are in progress when hsb is driven low by any means are given time (t delay ) to complete before the store operation is initiat ed. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. if the write latch is not set, hsb is not driven low by the device. however, any of the sram read and write cycles are inhibited until hsb is returned high by the host microcon- troller or another external source. during any store operation, rega rdless of how it is initiated, the device continues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after the hsb pin returns high. leave the hsb uncon- nected if it is not used. hardware recall (power-up) during power-up or after any low-power condition (v cc preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 11 of 36 table 1. mode selection ce [10] we oe ble , bhe / b a , b b, b c, b d [11] a 15 - a 0 [12] mode i/o power h x x x x not selected output high z standby l h l l x read sram output data active l l x l x write sram input data active l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [13] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [13] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [13] l h l x 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [13] notes 10. the tsop ii package is offered in single ce . tsop i, and bga packages are offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). 11. ble , bhe are applicable for the 16 configuration and b a , b b, b c, b d are applicable for the 32 configuration only. 12. while there are 21 address lines on the cy14x116l (20 address lines on the cy14x116n and 19 address lines on the cy14x116s), only 13 address lines (a 14 ?a 2 ) are used to control software modes. the remaining address lines are don?t care. 13. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a nonvolatile operation. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 12 of 36 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce or oe controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual software store operation must be performed to save the autostore state through subs equent power-down cycles. the part comes from the factory with autostore enabled and 0x00 written in all cells. data protection the cy14x116l/cy14x116n/cy14x116s protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low-voltage condition is detected when v cc is less than v switch. if the cy14x116l/cy14x116n/cy14x116s is in a write mode at power-up (both ce and we are low), after a recall or store, the write is inhibited until the sram is enabled after t lzhsb (hsb to output active). this protects against inadvertent writes during power-up or brownout conditions. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 13 of 36 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c maximum accumulated storage time at 150 ? c ambient temperature .................................. 1000 h at 85 ? c ambient temperature.................... ............. 20 years maximum junction temperature .................................. 150 ? c supply voltage on v cc relative to v ss cy14b116x: ................................................?0.5 v to +4.1 v cy14e116x: ................................................?0.5 v to +7.0 v voltage applied to outputs in high-z state...................................... ?0.5 v to v cc + 0.5 v input voltage .........................................?0.5 v to vcc + 0.5 v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. .1.0 w surface mount lead soldering temperature (3 seconds)......... .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) ..... 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current .................................................... > 140 ma operating range product range ambient temperature (t a ) v cc cy14b116x industrial ?40 ? c to +85 ? c 2.7 v to 3.6 v cy14e116x 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [14] max unit v cc power supply cy14b116x 2.7 3.0 3.6 v cy14e116x 4.5 5.0 5.5 v i cc1 average v cc current values obtained without output loads (i out = 0 ma) t rc = 25/30 ns ? ? 95 ma t rc = 45 ns ? ? 75 ma i cc2 average v cc current during store all inputs don?t care, v cc = v cc (max). average current for duration t store ??10ma i cc3 average v cc current at t rc = 200 ns, v cc (typ), 25 c all inputs cycling at cmos levels. values obtained without output loads (i out = 0 ma). ?50 ?ma i cc4 [15] average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??6ma i sb v cc standby current ce > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). ?standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. t rc = 25/30 ns ? ? 650 ? a t rc = 45 ns ? ? 500 ? a i zz sleep mode current all inputs are static at cmos level ? ? 10 ? a i ix [16] input leakage current (except hsb ) v cc = v cc (max), v ss < v in < v cc ?1 ? +1 ? a input leakage current (for hsb ) v cc = v cc (max), v ss < v in < v cc ?100 ? +1 ? a notes 14. typical values are at 25 c, v cc = v cc (typ). not 100% tested. 15. this parameter is only guaranteed by design and is not tested. 16. the hsb pin has i out = -2 ua for v oh of 2.4 v when both active high and low driver s are disabled. when they are enabled standard v oh and v ol are valid. this parameter is characterized but not tested. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 14 of 36 i oz off state output leakage current v cc = v cc (max), v ss < v out < v cc , ce or oe > v ih or ble , bhe /b a , b b, b c, b d > v ih or we < v il ?1 ? +1 ? a v ih input high voltage 2.0 ? v cc + 0.5 v v il input low voltage v ss ? 0.5 ? 0.8 v v oh output high voltage i out = ?2 ma 2.4 ? ? v v ol output low voltage i out = 4 ma ? ? 0.4 v v cap [17] storage capacitor between v cap pin and v ss 19.8 22.0 82.0 ? f v vcap [18, 19] maximum voltage driven on v cap pin by the device v cc = v cc (max) ? ? 5.0 v data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000,000 cycles capacitance in the following table, the capacitance parameters are listed. [19] parameter description test conditions max (all packages except 165-fbga) max (165-fbga package) unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = v cc (typ) 810pf c io input/output capacitance 8 10 pf c out output capacitance 8 10 pf thermal resistance in the following table, the thermal resistance parameters are listed. [19] parameter description test conditions 44-tsop ii 48-tsop i 54-tsop ii 165-fbga unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 44.6 35.6 41.1 15.6 ? c/w ? jc thermal resistance (junction to case) 2.4 2.33 4.6 2.9 ? c/w dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [14] max unit notes 17. min v cap value guarantees that there is a sufficient charge available to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. 18. maximum voltage on v cap pin (v vcap ) is provided for guidance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage 19. these parameters are only guaranteed by design and are not tested. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 15 of 36 figure 9. ac test loads and waveforms for 3 v (cy14b116x): for 5 v (cy14e116x): 3.0 v output c l r1 r2 789 ? 3.0 v output c l r1 r2 789 ? 577 ? 577 ? for tristate specs 5 pf 30 pf 5.0 v output c l r1 r2 512 ? 5.0 v output c l r1 r2 512 ? 963 ? 963 ? for tristate specs 5 pf 30 pf ac test conditions cy14b116x cy14e116x input pulse levels 0 v to 3 v 0 v to 3 v input rise and fall times (10%?90%) < 3 ns < 3 ns input and output timing reference levels 1.5 v 1.5 v preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 16 of 36 ac switching characteristics over the operating range [20] parameters description 25 ns 30 ns 45 ns unit cypress parameter alt parameter min max min max min max sram read cycle t ace t acs chip enable access time ? 25 ? 30 ? 45 ns t rc [22] t rc read cycle time 25 ? 30 ? 45 - ns t aa [23] t aa address access time ? 25 ? 30 ? 45 ns t doe t oe output enable to data valid ? 12 ? 14 ? 20 ns t oha [23] t oh output hold after address change 3 ? 3 ? 3 ? ns t lzce [24] t lz chip enable to output active 3 ? 3 ? 3 ? ns t hzce [21, 24] t hz chip disable to output inactive ? 10 ? 12 ? 15 ns t lzoe [24] t olz output enable to output active 0 ? 0 ? 0 ? ns t hzoe [21, 24] t ohz output disable to output inactive ? 10 ? 12 ? 15 ns t pu [24] t pa chip enable to power active 0 ? 0 ? 0 ? ns t pd [24] t ps chip disable to power standby ? 25 ? 30 ? 45 ns t dbe byte enable to data valid ? 12 ? 14 ? 20 ns t lzbe [24] byte enable to output active 0 ? 0 ? 0 ? ns t hzbe [21, 24] byte disable to output inactive ? 10 ? 12 ? 15 ns sram write cycle t wc t wc write cycle time 25 ? 30 ? 45 ? ns t pwe t wp write pulse width 20 ? 24 ? 30 ? ns t sce t cw chip enable to end of write 20 ? 24 ? 30 ? ns t sd t dw data setup to end of write 10 ? 14 ? 15 ? ns t hd t dh data hold after end of write 0 ? 0 ? 0 ? ns t aw t aw address setup to end of write 20 ? 24 ? 30 ? ns t sa t as address setup to start of write 0 ? 0 ? 0 ? ns t ha t wr address hold after end of write 0 ? 0 ? 0 ? ns t hzwe [21, 24, 25] t wz write enable to output disable ? 10 ? 12 - 15 ns t lzwe [24] t ow output active after end of write 3 ? 3 ? 3 ? ns t bw byte enable to end of write 20 ? 24 ? 30 ? ns notes 20. test conditions assume a signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc (typ), and output loading of the specified i ol /i oh and 30 pf load capacitance as shown in figure 9 . 21. t hzce , t hzoe , t hzbe and t hzwe are specified with a load capacitance of 5 pf. transition is measured 200 mv from the steady state output voltage. 22. we must be high during sram read cycles. 23. device is continuously selected with ce , oe and ble , bhe /b a , b b, b c, b d low. 24. these parameters are only guaranteed by design and are not tested. 25. if we is low when ce goes low, the outputs remain in the high impedance state. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 17 of 36 figure 10. sram read cycle 1: address controlled [26, 27, 28 ] figure 11. sram read cycle 2: ce and oe controlled [26, 28] address data output address valid previous data valid output data valid t rc t aa t oha address valid address data output output data valid standby active high impedance ce oe i cc t hzce t rc t ace t aa t lzce t doe t lzoe t dbe t lzbe t pu t pd t hzbe t hzoe ble, bhe /b a , b b , b c , b d [30] [29] notes 26. we must be high during sram read cycles. 27. device is continuously selected with ce , oe and ble , bhe /b a , b b, b c, b d low. 28. hsb must remain high during read and write cycles. 29. ble , bhe are applicable for the 16 configuration and b a , b b, b c, b d are applicable for the 32 configuration only. 30. tsop ii package is offered in single ce and bga package is offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 18 of 36 figure 12. sram write cycle 1: we controlled [32, 34, 36] figure 13. sram write cycle 2: ce controlled [32, 34, 36] data output data input input data valid high impedance address valid address previous data t wc t sce t ha t bw t aw t pwe t sa t sd t hd t hzwe t lzwe we ce ble, bhe /b a , b b , b c , b d 35 31 data output data input input data valid high impedance address valid address t wc t sd t hd ble, bhe we ce t sa t sce t ha t bw t pwe /b a , b b , b c , b d 35 31 notes 31. ble , bhe are applicable for the 16 configuration and b a , b b, b c, b d are applicable for the 32 configuration only. 32. if we is low when ce goes low, the outputs remain in the high impedance state. 33. we must be high during sram read cycles. 34. hsb must remain high during read and write cycles. 35. tsop ii package is offered in single ce . tsop i and bga packages are offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). 36. ce or we must be > v ih during address transitions. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 19 of 36 figure 14. sram write cycle 3: bhe , ble / b a , b b, b c, b d controlled [38, 39, 40] data output data input input data valid high impedance address valid address t wc t sd t hd we ce t sce t sa t bw t ha t aw t pwe ble, bhe /b a , b b , b c , b d 41 37 notes 37. ble , bhe are applicable for the 16 configuration and b a , b b, b c, b d are applicable for the 32 configuration only. 38. if we is low when ce goes low, the outputs remain in the high impedance state. 39. hsb must remain high duri ng read and write cycles. 40. ce or we must be > v ih during address transitions. 41. tsop ii package is offered in single ce . tsop i and bga packages are offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 20 of 36 autostore/power-up recall characteristics over the operating range parameter description min max unit t hrecall [42] power-up recall duration ? 30 ms t store [43] store cycle duration ? 8 ms t delay [44, 45] time allowed to comple te sram write cycle ? 25 ns v switch low-voltage trigger level cy14b116x ? 2.65 v cy14e116x ? 4.40 v t vccrise [45] v cc rise time 150 ? ? s v hdis [45] hsb output disable voltage ? 1.9 v t lzhsb [45] hsb to output active time ? 5 ? s t hhhd [45] hsb high active time ? 500 ns figure 15. autostor e or power-up recall [46] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t hrecall t hrecall hsb out autostore power-up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power -down autostore note note note note v cc 43 43 47 47 notes 42. t hrecall starts from the time v cc rises above v switch. 43. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 44. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 45. these parameters are only guaranteed by design and are not tested. 46. read and write cycles are ignored during store, recall, and while v cc is below v switch. 47. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 21 of 36 sleep mode characteristics over the operating range parameter description min max unit t wake sleep mode exit time (zz high to first access after wakeup) ? 30 ms t sleep sleep mode enter time (zz low to ce don?t care) ? 8 ms t zzl zz active low time 50 ? ns t wezz last write to sleep mode entry time 0 ? ? s t zzh zz active to dq hi-z time ? 70 ns figure 16. sleep mode [48] wake t v zz we data dq t sleep t zzh t hrecall v switch v switch cc read & write inhibited (rwi) power-up recall read & write power -down autostore sleep entry t wezz sleep sleep exit read & write note 48. device initiates sleep routine and enters into sleep mode after t sleep duration. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 22 of 36 software controlled store and recall characteristics over the operating range [49, 50] parameter description 25 ns 30 ns 45 ns unit min max min max min max t rc store/recall initiation cycle time 25 ? 30 ? 45 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t cw clock pulse width 20 ? 24 ? 30 ? ns t ha address hold time 0 ? 0 ? 0 ? ns t recall recall duration ? 600 ? 600 ? 600 ? s t ss [51, 52] soft sequence processing time ? 500 ? 500 ? 500 ? s figure 17. ce and oe controlled software store and recall cycle [50] figure 18. autostore enable and disable cycle t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t store /t recall t hhhd t lzhsb high impedance address #1 address #6 address ce oe hsb (store only) dq (data) rwi t delay note [53] [54] t rc t rc t sa t cw t cw t sa t ha t lzce t hzce t ha t ha t ha t delay address #1 address #6 address ce oe dq (data) t ss note rwi [53] [54] notes 49. the software sequence is clocked with ce controlled or oe controlled reads. 50. the six consecutive addresses must be read in the order listed in ta b l e 1 . we must be high during all six consecutive cycles. 51. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister command. 52. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the specif ic command. 53. tsop ii package is offered in single ce . tsop i and bga packages are offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). 54. dq output data at the sixth read may be invalid since the output is disabled at t delay time. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 23 of 36 hardware store characteristics over the operating range parameter description min max unit t dhsb hsb to output active time when write latch not set ? 25 ns t phsb hardware store pulse width 15 ? ns figure 19. hardware store cycle [55] figure 20. soft sequence processing [56, 57] ~ ~ hsb (in) hsb (out) rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t phsb hsb pin is driven high to v cc only by internal 100 k : resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set address #1 address #6 address #1 address #6 soft sequence command t ss t ss ce address v cc t sa t cw soft sequence command t cw 58 notes 55. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 56. this is the amount of time it takes to take action on a soft sequence command. vcc power must remain high to effectively reg ister command. 57. commands such as store and recall lock out i/o until operation is complete which further incr eases this time. see the specif ic command. 58. tsop ii package is offered in single ce . tsop i and bga packages are offered in dual ce options. in this datasheet, for a dual ce device, ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other cases ce is high. intermediate voltage levels are not permitted on any of the chip enable pins (ce for the single chip enable device; ce 1 and ce 2 for the dual chip enable device). preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 24 of 36 truth table for sram operations hsb should remain high for sram operations. for 8 configuration single chip enable option (44-pin tsop ii package) ce we oe inputs and outputs mode power h x x high-z deselect/power-down standby l h l data out (dq 0 ?dq 7 ) read active l h h high-z output disabled active ll xdata in (dq 0 ?dq 7 ) write active for 8 configuration dual chip enable option (48-pin tsop i package) ce 1 ce 2 we oe inputs and outputs mode power h x x x high-z deselect/power-down standby x l x x high-z deselect/power-down standby l h h l data out (dq 0 ?dq 7 ) read active l h h h high-z output disabled active l h l x data in (dq 0 ?dq 7 ) write active for 16 configuration single chip enable option (54-pin tsop ii package) ce we oe ble bhe inputs and outputs mode power h x x x x high-z deselect/power-down standby l x x h h high-z output disabled active lhllldata out (dq 0 ?dq 15 ) read active l h l l h data out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z read active l h l h l data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z read active l h h x x high-z output disabled active l l x l l data in (dq 0 ?dq 15 ) write active l l x l h data in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z write active l l x h l data in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z write active preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 25 of 36 for 16 configuration dual chip enable option (48-pin tsop i package and 165-ball fbga package) ce 1 ce 2 we oe ble bhe inputs and outputs mode power h x x x x x high-z deselect/power-down standby x l x x x x high-z deselect/power-down standby l h x x h h high-z output disabled active l h h l l l data out (dq 0 ?dq 15 ) read active lhhllhdata out (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z read active l h h l h l data out (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z read active l h h h x x high-z output disabled active l h l x l l data in (dq 0 ?dq 15 ) write active lhlxlhdata in (dq 0 ?dq 7 ); dq 8 ?dq 15 in high-z write active l h l x h l data in (dq 8 ?dq 15 ); dq 0 ?dq 7 in high-z write active for 32 configuration dual chip enable option (165-ball fbga package) ce 1 ce 2 we oe b a b b b c b d dq 0 ?dq 7 dq 8 ?dq 15 dq 16 ?dq 23 dq 24 ?dq 31 mode power h x x x x x x x high-z high-z high-z high-z deselect/ power down standby x l x x x x x x high-z high-z high-z high-z deselect/ power down standby l h x x x x x x high-z high-z high-z high-z selected active l h h l l l l l data out data out data out data out read all bits active l h h l l h h h data out high-z high-z high-z read active l h h l h l h h high-z data out high-z high-z read active l h h l h h l h high-z high-z data out high-z read active l h h l h h h l high-z high-z high-z data out read active l h l x l l l l data in data in data in data in write all bits active l h l x l h h h data in high-z high-z high-z write active l h l x h l h h high-z data in high-z high-z write active l h l x h h l h high-z high-z data in high-z write active l h l x h h h l high-z high-z high-z data in write active l h h h x x x x high-z high-z high-z high-z output disabled active preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 26 of 36 ordering information speed (ns) ordering code package diagram package type operating range 25 cy14b116l-zs25xi 51-85087 44-pin tsop ii industrial cy14b116l-zs25xit 51-85087 44-pin tsop ii cy14e116l-zs25xi 51-85087 44-pin tsop ii cy14e116l-zs25xit 51-85087 44-pin tsop ii cy14b116n-zsp25xi 51-85160 54-pin tsop ii cy14e116n-zsp25xi 51-85160 54-pin tsop ii cy14b116n-bz25xi 51-85195 165-ball fbga CY14B116N-BZ25XIT 51-85195 165-ball fbga cy14b116s-bz25xi 51-85195 165-ball fbga cy14b116s-bz25xit 51-85195 165-ball fbga cy14e116s-bz25xi 51-85195 165-ball fbga cy14e116s-bz25xit 51-85195 165-ball fbga 30 cy14b116l-z30xi 51-85183 48-pin tsop i cy14b116l-z30xit 51-85183 48-pin tsop i cy14e116l-z30xi 51-85183 48-pin tsop i cy14e116l-z30xit 51-85183 48-pin tsop i cy14b116n-z30xi 51-85183 48-pin tsop i cy14b116n-z30xit 51-85183 48-pin tsop i cy14e116n-z30xi 51-85183 48-pin tsop i cy14e116n-z30xit 51-85183 48-pin tsop i 45 cy14b116l-zs45xi 51-85087 44-pin tsop ii cy14b116l-zs45xit 51-85087 44-pin tsop ii cy14e116l-zs45xi 51-85087 44-pin tsop ii cy14e116l-zs45xit 51-85087 44-pin tsop ii cy14b116l-z45xi 51-85183 48-pin tsop i cy14b116l-z45xit 51-85183 48-pin tsop i cy14e116l-z45xi 51-85183 48-pin tsop i cy14e116l-z45xit 51-85183 48-pin tsop i cy14b116n-z45xi 51-85183 48-pin tsop i cy14b116n-z45xit 51-85183 48-pin tsop i cy14b116n-zsp45xi 51-85160 54-pin tsop ii cy14b116n-zsp45xit 51-85160 54-pin tsop ii cy14e116n-z45xi 51-85183 48-pin tsop i cy14e116n-z45xit 51-85183 48-pin tsop i cy14b116n-bz45xi 51-85195 165-ball fbga cy14b116n-bz45xit 51-85195 165-ball fbga cy14b116s-bz45xi 51-85195 165-ball fbga cy14b116s-bz45xit 51-85195 165-ball fbga all parts are pb-free. contact your local cypress sales representative for availability of these parts. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 27 of 36 ordering code definitions option: t - tape & reel blank - std. speed: 25 - 25 ns data bus: l - 8 density: 116 - 16-mbit voltage: b - 3.0 v cypress cy14 b 116 l - zs 25 x i t nvsram 14 - temperature: i - industrial (?40 to 85 c) pb-free package: zs p- 44-tsop ii zsp - 54-tsop ii bza - 165-fbga n - 16 s - 32 30 - 30 ns 45 - 45 ns e - 5.0 v zs p- 48-tsop i preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 28 of 36 package diagrams figure 21. 44-pin tsop ii package outline (51-85087) 51-85087 *e preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 29 of 36 figure 22. 48-pin tsop i package outline (51-85183) package diagrams (continued) 51-85183 *c preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 30 of 36 figure 23. 54-pin tsop ii package outline (51-85160) package diagrams (continued) 51-85160 *e preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 31 of 36 figure 24. 165-ball fbga (15 mm 17 mm 1.40 mm) package outline (51-85195) package diagrams (continued) 51-85195 *c preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 32 of 36 acronyms document conventions units of measure all errata for this product are fixed, effective date code 1431 (yy=14, ww=31). for more informat ion, refer to datasheet 001-67 793 rev. *j, or contact cypress technical support at http://www.cypre ss.com/support . acronym description cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jesd jedec standards nvsram nonvolatile static random access memory rohs restriction of hazardous substances rwi read and write inhibited tsop ii thin small outline package symbol unit of measure c degrees celsius hz hertz kbit kilobit khz kilohertz k ? kilohm ? a microampere ma milliampere ? f microfarad mbit megabit mhz megahertz ? s microsecond ms millisecond ns nanosecond pf picofarad v volt ? ohm w watt preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 33 of 36 document history page document title: cy14b116l/cy14b116n/cy14b116s/cy14e1 16l/cy14e116n/cy14e116s, 16-mbit (2048 k 8/1024 k 16/512 k 32) nvsram document number: 001-67793 rev. ecn no. orig. of change submission date description of change ** 3186783 gvch 03/02/2011 new datasheet. *a 3202367 gvch 03/22/2011 updated dc electrical characteristics (changed maximum value of i sb parameter from 3 ma to 500 a). *b 3459888 gvch 12/09/2011 changed status from ?advance? to ?preliminary?. updated pinouts (updated figure 5 and figure 6 ). updated pin definitions (updated zz pin description). updated dc electrical characteristics (changed maximum value of i cc1 parameter from 70 ma to 95 ma for t rc = 25 ns, changed maximum value of i cc1 parameter from 50 ma to 75 ma for t rc = 45 ns, changed typical value of i cc3 parameter from 35 ma to 50 ma, changed maximum value of i cc4 parameter from 10 ma to 6 ma , changed maximum value of i sb parameter from 500 a to 650 a, added v cap parameter values for cy14c116x, changed minimum value of v cap parameter from 20 f to 19 f, changed typical value of v cap parameter from 27 f to 22 f respectively, added note 16 and referred the same note in v cap parameter). updated thermal resistance (added values). updated ac switching characteristics (added note 20 and referred the same note in parameters column). updated autostore/power-up recall characteristics (changed maximum value of t hrecall parameter from 40 ms to 60 ms for cy14c116x, changed maximum value of t hrecall parameter from 20 ms to 30 ms for cy14b116x/cy14e116x, changed maximum value of t wake parameter from 40 ms to 60 ms for cy14c116x, changed maximum value of t wake parameter from 20 ms to 30 ms for cy14b116x/cy14e116x). updated software controlled store and recall characteristics (changed maximum value of t recall parameter from 300 s to 600 s, changed maximum value of t ss parameter from 200 s to 500 s). updated ordering information (updated part numbers). updated package diagrams (to current revision). *c 3510173 gvch 01/27/2012 updated ordering information (removed cy14e116n-zs25xi and added cy14b116n-z25xi part number). updated in new template. *d 3733467 gvch 09/14/2012 updated device operation (added figure 8 under sleep mode ). updated maximum ratings (changed ?ambient temperature with power applied? to ?maximum junction temperature?). updated dc electrical characteristics (added v vcap parameter and its details, added note 18 and referred the same note in v vcap parameter, also referred note 19 in v vcap parameter). updated capacitance (changed maximum value of c in and c out parameters from 7 pf to 11.5 pf). added sleep mode and figure 16 (corresponding to sleep mode). updated package diagrams (spec 51-85087 (changed revision from *d to *e). preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 34 of 36 *e 4198509 gvch 01/23/2014 updated features : removed 2.5 v operating range voltage support. added 54-pin tsop ii package related information. updated logic block diagram updated device operation : updated autostore operation (power-down) : removed sentence ?the hsb signal is monitored by the system to detect if an autostore cycle is in progress.? updated dc electrical characteristics : updated test conditions of i sb parameter and also updated the corresponding values. changed maximum value of v ih parameter from ?v cc + 0.3 v? to ?v cc + 0.5 v?. updated v cap value from 20 uf to 19.8 uf. added note 20. updated capacitance : changed maximum value of c in and c out parameters from 11.5 pf to 8 pf. updated sleep mode : changed maximum value of t zzh parameter from 20 ns to 70 ns. updated figure 8 and figure 16 for more clarity. updated truth table for sram operations for more clarity. updated ordering information (updated part numbers). updated package diagrams : added 54-pin tsop ii package related information ( figure 23 ). *f 4303589 gvch 03/20/2014 updated thermal resistance : updated values of ? ja and ? jc parameters. updated in new template. completing sunset review. *g 4366689 gvch 05/01/2014 updated sleep mode : updated description. updated dc electrical characteristics : removed ?rtc running on backup power supply? in test conditions of i zz parameter. added note 14 and 25 . updated ordering information (updated part numbers (added part numbers namely cy14b116n-zsp45xi, cy14b116n-zsp45xit, cy14e116s-bz25xi and cy14e116s-bz25xit)). added . *h 4409843 gvch 06/17/2014 updated dc electrical characteristics : updated maximum value of v vcap parameter to 5.0 v for cy14b116x and cy14e116x. *i 4417851 gvch 06/24/2014 added footnote 15 capacitance : updated c in and c out value from 8 pf to 10 pf for 165-fbga package added c io parameter updated ordering code definitions to add package code for 48-tsop i package *j 4432183 gvch 07/07/2014 dc electrical characteristics : updated maximum value of v cap parameter from 120.0 ? f to 82.0 ? f document history page (continued) document title: cy14b116l/cy14b116n/cy14b116s/cy14e1 16l/cy14e116n/cy14e116s, 16-mbit (2048 k 8/1024 k 16/512 k 32) nvsram document number: 001-67793 rev. ecn no. orig. of change submission date description of change preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s document #: 001-67793 rev. *l page 35 of 36 *k 4456803 zsk 07/31/2014 removed errata section. added a note at the end of the document mentioning when the errata items were fixed. *l 4562106 gvch 11/05/2014 added related documentation hyperlink in page 1. updated package diagram 51-85160 to current revision. document history page (continued) document title: cy14b116l/cy14b116n/cy14b116s/cy14e1 16l/cy14e116n/cy14e116s, 16-mbit (2048 k 8/1024 k 16/512 k 32) nvsram document number: 001-67793 rev. ecn no. orig. of change submission date description of change document #: 001-67793 rev. *l revised november 5, 2014 page 36 of 36 all products and company names mentioned in this document are the trademarks of their respective holders. preliminary cy14b116l/cy14b116n/cy14b116s cy14e116l/cy14e116n/cy14e116s ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc 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